A driving signal having an overly high level output by a gate driving circuit would cause breakdown of gate oxide layers of a field effect transistor (FET). Therefore, the protection of the gate oxide layers of a driven element against breakdown must be taken into consideration when designing a gate driving circuit. Generally, a Zener diode or a linear regulator is applied to provide required clamping voltage level and electric current.
FIG. 1 shows a circuit 10 in which a Zener diode 12 is used to drive a p-type power transistor 13 so as to achieve the purpose of voltage clamping. In the circuit 10, a difference between an output voltage VOUT and a supply voltage VDD is limited to a breakdown voltage of the Zener diode, so as to achieve the output voltage clamping effect. However, since the Zener diode operates within a breakdown region when clamping the output voltage VOUT, there is direct current flowing through the Zener diode, and accordingly, relatively higher power consumption.
FIG. 2 show a circuit 20 in which a linear regulator 22 is used to drive a p-type power transistor 24 so as to achieve the purpose of voltage clamping. In the circuit 20, a negative feedback is utilized to lock a difference between the output voltage VOUT and the supply voltage VDD to a preset voltage level, so as to achieve the output voltage clamping effect. However, there is a preset voltage drop in the linear regulator 22, and therefore there is a quiescent direct current. In addition, the linear regulator 22 also has to provide high-speed transient current needed by gate signal level translation. Therefore, in this conventional way of voltage clamping, a large-area voltage-stabilizing capacitor 23 is required to stabilize the output voltage VOUT. As a result, a large chip area is occupied and an increased cost is required.